This is the second post regarding the 2019 UK graduation trip. Please refer to this link for the previous post regarding the trip.
During October of 2019, my family went to the UK to join the Commemoration Day to celebrate my graduation from Imperial College London as an undergraduate student. The post covers day 1 to day 5 of the trip. For day 6 to day 9, please refer to this link.
Assignment for ECEN 646 Homework 5 Problem 4. Coded in Python.
The project intends to provide a simple solution for those who wish to generate structured Verilog HDL code from a GUI and is suitable for those who just start working with FPGA and Verilog HDL.
Previously the contents of the website were generated locally then pushed to a GitHub repository. Now Travis CI is used to generate static files instead of the local machine.
The HDL Editor project is an extension to my undergraduate final year project. This article serves as a table of contents for the posts on re-creating and improving the project.
The courses for the academic year of 2019-2020 are listed as the following:
Previously the website was hosted on AWS S3 but now it is time to migrate to GitHub pages.